How to add additional delay in selected path?

Given your earlier threads about a divide-by-2 register, I suspect your present clock skew problem is for a cross-domain path with just the source or just the destination register using that divided clock. Recall the post I referred you to before at http://www.alteraforum.com/forum/showthread.php?p=2457#post2457 where the next-to-least-preferred option is this: "If you have hold violations going between domains, have the Fitter try to fix them by setting 'Optimize hold timing' to 'All paths'."

If you are not willing to change your divide-by-2 clock to a divide-by-2 clock enable (using the undivided clock) and can't use a PLL for the slower clock, then you might want to reconsider how you transfer data between clock domains. Maybe you can change to asynchronous transfers with handshaking if you are transferring a set of signals (like a bus) or use simple metastability synchronization registers if you are transferring data on individual signals that don't have to be synchronized to each other.