How to add additional delay in selected path?

Well you really should not have hold time issues in an FPGA. This is probably caused by unintentional clock skew in your design. But if the circuit really is what you want and is being analyzed as you desire, than you should check out:

Assignment->Settings->Fitter Settings and make sure "Optimize hold timing" is set to "All paths". This will allow the fitter to add the data delay you need. You may also want to turn on "Optimize fast-corner timing.