How to access On Chip Memory in VHDL

Hi guys,

I have the Problem, that i cant access On Chip Memory.

I´m using a DE0-Nano Board, with a Cyclone IV EP4CE22F17C6 FPGA.

I have generated the Memory with Qsys:

http://abload.de/thumb/qsysmemoryscreenshotq5bbv.png (http://abload.de/image.php?img=qsysmemoryscreenshotq5bbv.png)

Than I have used the Component in my VHDL Code.

I have filled the Initialization hex file wit 0x55 at every address.

Than I have tried, to transmit the value from Address 1 via UART.

But I only receive 0x00 :(

The UART part is working.

This is my VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART is
port(
        clk_50, Tast, RxD : in std_logic;
        TxD : out std_logic;
        LedBar : out std_logic_vector (7 downto 0);
        DIPSwitch : in std_logic_vector (7 downto 0);
        LEDGreen0 : out std_logic
        );
end UART;
Architecture UART_arch of UART IS
component UART_transmit is
port(
        clk, tx_start : in std_logic;
        TxD : out std_logic := '1';
        Tx_Data : in std_logic_vector (7 downto 0);
        busy : out std_logic
        );
end component UART_transmit;        
component UART_receive is
port(
        clk : in std_logic;
        Busy : out std_logic;
        RxD : in std_logic := '1';
        Rx_Data : out std_logic_vector (7 downto 0)
        );
end component UART_receive;
component OCMemory is
        port (
            clk_clk       : in  std_logic                    := 'X';             -- clk
            reset_reset   : in  std_logic                    := 'X';             -- reset
            s1_address    : in  std_logic_vector(7 downto 0) := (others => 'X'); -- address
            s1_clken      : in  std_logic                    := 'X';             -- clken
            s1_chipselect : in  std_logic                    := 'X';             -- chipselect
            s1_write      : in  std_logic                    := 'X';             -- write
            s1_readdata   : out std_logic_vector(7 downto 0);                    -- readdata
            s1_writedata  : in  std_logic_vector(7 downto 0) := (others => 'X')  -- writedata
        );
    end component OCMemory;
        Signal DataToTransmit : std_logic_vector(7 downto 0) := "00110000";
        Signal ChipSelect : std_logic := '0';
        
Begin
u0 : component OCMemory
        port map (
            clk_clk       => clk_50,       --   clk.clk
            reset_reset   => '0',   -- reset.reset
            s1_address    => "00000001",    --    s1.address
            s1_clken      => '1',      --      .clken
            s1_chipselect => chipselect, --      .chipselect
            s1_write      => '0',      --      .write
            s1_readdata   => DataToTransmit,   --      .readdata
            s1_writedata  => "00000000"   --      .writedata
        );
T0  : UART_transmit PORT MAP(clk => clk_50, 
                                      TxD => TxD,
                                      Tx_Data => DataToTransmit,
                                      Tx_start => NOT Tast);
                                      
R0 : UART_receive PORT MAP(clk => clk_50 ,
                                    RxD => RxD,
                                    Rx_Data => LEDBar);
                                    
                                    
process (clk_50)
variable cnt : integer range 0 to 15;
begin
    if rising_edge(clk_50) then
        if cnt < 3 then 
            cnt := cnt + 1;
        else
            cnt := 0;
            chipselect <= NOT chipSelect;
        end if;
    end if;
end process;    
                    
LedGreen0 <= chipselect;                    
                                
end Architecture;        

Can anyone help me please?

I cant find help with google.

I had only found examples wit the NIOSII.

Am I using the Memory correct?

Please excuse my bad english.

Greets

Olaf