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Altera_Forum's avatar
Altera_Forum
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13 years ago

how to accelerate the compilation speed

I am currently working on a big project(at least for me ),there are some big parts of the project are verified and works fine ,but every time i did some modification to the part that i work on ,the w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I have a further question on design partitioning. Scenario : I have a working NIOS subsystem created in Qsys that I am not going to use for a while. I instantiate the NIOS subsystem at my top-level, fully-synthesized the design and then created a design partition for the NIOS subsystem ONLY (along with a logic-lock region). I set the Netlist type to "Post-Fit". Fully synthesized the design again.

But, when I make simple (adding a two-input XOR) changes to my top-level, the synthesis procedure still compiles the entire NIOS subsystem. The Partition Merge report shows "Source File" for "Netlist Type Used" because it says "detected changes in source file". I have however not even touched the NIOS subsystem.

So I need help on understanding why the synthesis tool keeps recompiling the NIOS subsystem in spite of my design partition (and no manual changes to the subsystem on my part).

Let me know if you need further details on my design, thanks.

Bharath

PS : For now, I have removed all design partitions and commented out the subsystem to speed up synthesis, place-and-route etc. but I would really like to understand what is going on.