Forum Discussion
Ruturaj_D_Intel
New Contributor
New ContributorHow TimeQuest analyzes path though the latch?
I want to know if TimeQuest analyzes path through the latch. If there is latch in the design how do I make sure that timing gets analyzed by static timing analyzer. In my design I see that tool gives...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
If you use asynchronous load and data signals to implement a latch. These nodes will be treated as latches during timing analysis. The Timing Analyzer may not correctly analyze designs containing latches. In some cases, timing analysis does not completely model latch timing . As a best practice, avoid latches unless required by the design and you fully understand the impact. It is recommended to change your design to remove the latches whenever possible.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-design-recommendations.pdf (Chapter 2.5 Register and Latch Coding Guidelines)
Thanks.
