How TimeQuest analyzes path though the latch?

Hi,

If you use asynchronous load and data signals to implement a latch. These nodes will be treated as latches during timing analysis. The Timing Analyzer may not correctly analyze designs containing latches. In some cases, timing analysis does not completely model latch timing . As a best practice, avoid latches unless required by the design and you fully understand the impact. It is recommended to change your design to remove the latches whenever possible.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-design-recommendations.pdf (Chapter 2.5 Register and Latch Coding Guidelines)

Thanks.