Forum Discussion
Altera_Forum
Honored Contributor
17 years agoThank for you help
If you look my attach design in cpd_top.vhd i recover a clock (rx clock) with input DIN and SIN. And for my design i need path delay rx clock greather than path DIN. therefore i want expand path of DIN. i need respect the rule PATH DIN < PATH rx_clk - setup flip flop thank you excuse for my bad english