how set minimu delay (constraint) with TIMEQUEST

1) I saw this was last compiled in Q6.1. I used Q8.0 and would recommend upgrading, as TimeQuest has steadily improved with each release. Nothing overly drastic, but a lot of usability enhancements.

2) Assignments -> Settings -> Timing Analysis -> Use TimeQuest radio button. Right now you have selected the Classic Timing Analyzer, which means to completely ignore your .sdc file.

3) Assignments -> Settings -> Fitter -> Optimize Hold Timing -> All Paths.

It's default value is to just add delays for I/O paths, i.e. it won't add delay to fix hold requirements internally. The reason this is the default is designers often make gated clocks that introduce all sorts of difficult hold requirements, where it's best for the designer to change the code(use a PLL, clock enable or altclkctrl, depending on what they're doing), rather than have Quartus fix it. Otherwise Quartus will tend to mask the problem.

4) Finally, I just wanted to point out that set_min_delay and set_max_delay assignments do take into account clock delays(skew). Many people don't realize this, and think it's a point to point assignment. The fact that it uses clock delays is a very good thing, since the relationship between two registers is dependent on clock delays as much as the data delay between them. You'll see this once you analyze the path in TQ.