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DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

How Quartus route clock after pll?

Hi, If i have the same clock going to two registers, Quartus will ensure that the clock arrives at these two registers at the same time for synchronous design. If I have two clocks with the same fr...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi @DNguy4​ , if you have 2 independent clock, most probably PLL will route them to 2 different GCLKs. The skew between each GCLK is minimum. If you would like to constrain, you can constrain them to different GCLK and see which GCLK combination has the lowest skew.