How does quartus fit design without SDC?

The first issue you will have is that Quartus will assume a default frequency for your clocks - I believe it sets unconstrained clock to 1GHz. After that, pretty much anything you have will fail timing. I don't know how Quartus will treat the PLL IP.

Yes, as mentioned, without an SDC file, it will set all absolute clocks to 1 GHz. For PLLs, it will run derive_pll_clocks automatically, so it will generate the PLL output clocks for you. At a minimum in your SDC file, you should have create_clock statements for all input clocks, add derive_pll_clocks, and add derive_clock_uncertainty. If all of your input clocks feed PLLs, then you don't need to add the create_clock statements. Instead, when you add the derive_pll_clocks, use the -create_base_clocks option.