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Altera_Forum
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14 years ago

How does quartus fit design without SDC?

If there isn't any sdc file, how does quartus do fitter ? if I don't set derive_pll_clocks, can quartus conclude any clock information from setting of mega IP PLL?
Altera_Forum's avatar
Altera_Forum
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14 years ago

The first issue you will have is that Quartus will assume a default frequency for your clocks - I believe it sets unconstrained clock to 1GHz. After that, pretty much anything you have will fail timing. I don't know how Quartus will treat the PLL IP.