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When one writes VHDL it is possible to use testbench to determine if the code functions as intended, with C/C++ program one can also use test cases. How does one verify timing constraints? How does one know if they have bug in them?
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if you mean sdc syntax check then the tool kindly stops with a strange message saying "cannot fit design" if it encounters syntax error.
additionally it warns if it doesn't find a path in sdc command.
If you mean checking sdc commands functionally then it is your responsibility as designer to specify the correct constraints.
most difficult ones are multicycle and io
multicycle can be checked by adding after statement for one clock delay or more if feasible in your functional simulation provided you have a pass/fail flag.
But it needs to be random as well across various registers and this by itself could be too laborious but is ok for few registers case.
The alternative to STA(static timing analysis) is timing simulation but still you need sdc constraints for the design to get correct delays. You then need pass/fail flag against a reference mode just as functional simulation. But timing simulation is way too length to be practical for any project. Even then your io behaviour depends on some other variables such as temperature/voltage and a check over all corners is not realistic with timing simulation.
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