How does one verify the SDC constraints?

One simple thing I do to "verify" timing constraints is to constrain the design in a way that I know WON'T meet timing (for example, set an input or output delay to a value that can't possibly be met). Then constrain the design in a way that can easily be met. In each case TimeQuest should indicate a pass or fail condition. If it doesn't, you know something is amiss. This won't catch everything, of course, but I've uncovered a number of errors this way, including errors in my own thinking about how a particular timing constraint works.