How does one verify the SDC constraints?

Good question. I think there are some tools that can do some verification(spyglass cdc) but I don't think they can fully test all cases. (If your data coming in changes every other clock cycle, a multicycle may be appropriate, but 3rd party tools can't know that). One thing I think that should be done is a random delay assignment, so if a path is is false path'd it can have some random delay throughout the simulation, and if it's a multicycle it can vary over the multicycle range. I don't create simulations so don't know how this is done, but curious if others do it. I've never heard anyone say they added a multicycle and the modified their testbench to test for this.