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Honored Contributor
Honored ContributorHow does one verify the SDC constraints?
When one writes VHDL it is possible to use testbench to determine if the code functions as intended, with C/C++ program one can also use test cases. How does one verify timing constraints? How does o...
Altera_ForumHonored Contributor
Honored ContributorYou can't "verify" in that way. You must be careful and considered when you apply timing constraints. I suggest peer review - get someone else to look over your constraints to ensure they make sense.
Quartus should identify invalid constraints - i.e. constraints that make no sense or have no relevance to the code you're compiling. Always address these warnings as it, almost certainly, means party of your design is not constrained. Also pay particular attention to constraints that are not met. This may simply point to an area of your logic Quartus is having difficulty with. However, it may point at an 'error' in a constraint - one that is poorly thought through and could never be achieved. Cheers, Alex
