Honored Contributor
Honored ContributorHey Tsuchi,
Yea I've got the "No CFI table found at address 0x02000000" Here is a screen shot of what I'm seeing. https://www.alteraforum.com/forum/attachment.php?attachmentid=8891 Im using Altera's Cyclone III development board. I'm only trying to talk to the flash part on there that is on the same bus as the SRAM. Here is a screen shot of my qsys. I'm connecting the CFI controller to the conduit bridge directly because I don't use the SRAM I don't think I need the pin sharer. https://www.alteraforum.com/forum/attachment.php?attachmentid=8892 All I want to do is store my quartus Nios ii core AND my C code from the nios ii eds for that core so that when I power on the development board the FPGA runs BOTH my nios core WITH the C code I wrote for it. Basically I"m trying to get to the point where I turn on the board and it powers up running my c code for the nios ii processor without having to be programmed all the time. This board doesn't have the epcs device but rather a spansion flash part. I've read through most of the documentation and it sounds like you can do this with the nios ii flash programmer, but it seems I'm currently stuck on trying to communicate to this flash part. My understanding was that I just build my quartus hardware project to include this CFI controller and the programmer should be able to talk to the cfi device. It looks like its almost working. I've also attached the board reference manual for this development board. If you look at the flash section on the left under "onboard memory" it shows the memory map on page 2-60. In my qsys design my flash memory goes from 0x0200 0000 to 0x03ff ffff, but the memory map says the user space is only 32MB from 0x0200 0000 to 0x03F9 FFFF. I'm not sure what I should be doing here. Should I only be using the user space or should I be putting this design (the nios ii hardware design and software design) in one of the FPGA design spaces? Why does it show the address in qsys as using everything above 0x0200 0000? Attached is the information regarding my flash part and it's control signals. I've verified all pin connections in pin planner are correct from fpga to flash via the signals generated with this qsys model so I am confident it isn't a pin to pin connection. Control signals in qsys: https://www.alteraforum.com/forum/attachment.php?attachmentid=8896 Control signals in schematics: https://www.alteraforum.com/forum/attachment.php?attachmentid=8897
