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BHunt11's avatar
BHunt11
Icon for New Contributor rankNew Contributor
5 years ago

How do I report powered-down transceivers and PLLs in Quartus Prime Standard?

I have an issue which looks like an xcvr_fpll_a10_0 may not be powered or is shut down. How can I confirm that all the PLLs are in fact powered on in Quartus?
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,

The workaround should works as the power on calibration process and user triggered re-calibration process using dynamic reconfig is the same.

I presume you are not using PCIe. This workaround only works for none PCIe protocol.

You can refer to transceiver power-on calibration and user re-calibration guideline in below user guide doc (chapter 7.3, page 583)

Another thing to mention is maybe you can use IOPLL instead of fPLL to provide the 100MHz clock to clkusr pin.

  • Pls try your best to take care of the clock signal quality that maybe impacted by your board rework.
  • I hope this rework is just temporary workaround while waiting for your board design fix in future.

Thanks.

Regards,

dlim

BHunt11's avatar
BHunt11
Icon for New Contributor rankNew Contributor
5 years ago

Thanks Deshi. I'm trying to get a PLL (the 500Mhz TX fPLL) to recalibrate first, and having trouble. I'm still a little confused about a few things.

1) In what order do I reconfigure the PLLs and PMA? I have two fPLLs: 100M CDR ref clock, and 500M TX ref clock. Each of these has the pll_cal_busy asserted in signaltap, after I poweron. The avalon reconfig clock comes from an external 100MHz clock pin.

2) I don't see any reset signal explicitly on these PLLs. (Except for the avalon reset.) How do I reset each one?

3) The transceiver PMA remains in reset until the fPLLs are up and running. I have not tried to take the transceiver out of reset.

4) I tried to use a JTAG Avalon master to control the reconfig interface on the 500M TX PLL. I see the waitrequest asserted when I inspect the avalon bus in signaltap, but I can't seem to arbitrate for access. I tried to do an 8bit write of 0x2 to address 0x0 (and 32b write), but in both cases the avalon bus hung forever.

5) I see the fPLL has an option "Enable Altera Debug Master" which is also called NPDME, but I have not found how to use it. I do not have this enabled in the fPLL. Is this required to drive the reconfig_* interface with a JTAG Avalon Master?

Thanks again,

BryanH