New Contributor
Regular ContributorHI,
So, I presume you had fixed the clkusr issue ?
For transceiver calibration register access, you can refer to below PHY user guide doc chapter 7 to learn about transceiver calibration process.
For transceiver calibration enable control, refer to table 300, chapter 7.2.2 targeting offset address 0x100 (page 579)
Thanks
Regards,
dlim
New ContributorI'm trying a simple rework, where I drive 100MHz out of a pin into CLKUSR. (So this clock is not available for initial powerup calibration.) My intention is to now force the PMA and the PLLs to recalibrate using their dynamic-reconfiguration interfaces.
I have a JTAG Avalon master driving the reconfig interface of the fPLL. Then, I start the user recalibration process.
Can you confirm whether this would work? Am I required to assert or deassert the PLL reset while using the reconfig interface?
