How do I get this tcl script to run?

No worries, I copied the file into a new proc like so. Didn't know tcl was that easy :)

proc date2hdl {input_fn output_fn } {#  Date2HDL version 0.1 HT-Lab 2003#  #  Useage: Date2HDL <input_filename>    <output_filename># #  Date2HDL will search for the string 'define/constant DATE_VECTOR_C and #  replace the constant with the current date.# #  VHDL (.vhd extention)#      constant DATE_VECTOR_C : std_logic_vector(12 downto 0):="0000000000000";#  Verilog (.v extention)#   `define DATE_VECTOR_C 13'b0000000000000# #  Date String format:#  Day 0..31, 5 bits#  Month 0..12, 4 bits#  Year 0..15, 4 bits#  Bit    12 11 10 09 08 07 06 05 04 03 02 01 00 #  Format   # #  set to 1 to print debugging info
set debug 1
#  Convert Decimal to Boolean String
proc dec2bool {decstring} {
    switch $decstring {
        00 {return "00000"}
        01 {return "00001"}
        02 {return "00010"}
        03 {return "00011"}
        04 {return "00100"}
        05 {return "00101"}
        06 {return "00110"}
        07 {return "00111"}
        08 {return "01000"}
        09 {return "01001"}
        10 {return "01010"}
        11 {return "01011"}
        12 {return "01100"}
        13 {return "01101"}
        14 {return "01110"}
        15 {return "01111"}
        16 {return "10000"}
        17 {return "10001"}
        18 {return "10010"}
        19 {return "10011"}
        20 {return "10100"}
        21 {return "10101"}
        22 {return "10110"}
        23 {return "10111"}
        24 {return "11000"}
        25 {return "11001"}
        26 {return "11010"}
        27 {return "11011"}
        28 {return "11100"}
        29 {return "11101"}
        30 {return "11110"}
        31 {return "11111"}
        default {
            puts "Error in dec2bool proc, can't convert $decstring"
         #     exit
         }        
    }                        
}
puts "Date2HDL version 0.1 WWW.HT-LAB.COM"
#  Check number of argments# if {!=2} {#     puts "Useage : Date2HDL <source_filename> <destination_filename>"#     puts "Example: Date2HDL top.vhd top_date.vhd"#     puts "Example: Date2HDL main.v mainsynth.v"#      exit# }
#  Check for HDL type
if { == 0} {
    set hdl_type "Verilog"
    set search_string {\s*`define\s*DATE_VECTOR_C}
} else {
    set hdl_type "VHDL"
    set search_string {\s*constant\s*DATE_VECTOR_C}
}
if {$debug} { puts "HDL Type=$hdl_type" }
#  Read Date
set current_day    -format "%d"]
set current_month  -format "%m"]
set current_year   -format "%y"]
set bool_date " 1 4] 1 4]"
if {$debug} {
    puts "Date: $current_day -> "
    puts "Date: $current_month -> "
    puts "Date: $current_year -> "
    puts "Date: $bool_date"
}
#  Open Source File
if } msg] {
    puts $msg
    exit
}
#  Open Destination file
if } msg] {
    puts $msg
    exit
}
#  Scan for: DATE_VECTOR_C string & replace
while {!} {
    if {>=0} {
        if {} {
            puts "Replacing :$line"
            if {$hdl_type=="VHDL"} {
                regexp {(.*?")} $line ignore leftstring
                puts "With      :$leftstring$bool_date\";"
                puts $fpw "$leftstring$bool_date\";"
            } else {
                regexp {(.*?'b)} $line ignore leftstring
                puts "With      :$leftstring$bool_date"
                puts $fpw "$leftstring$bool_date"
            }
        } else {
            puts $fpw $line
        }
    }    
}
close $fp
close $fpw
puts "Done.."
}