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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

how can we generate post mapping netlist file when using STRATIX IV

Hello,

I usually generate a Verilog Quartus Mapping file (vqm) with a FPGA Cyclone II in order to win time of Analysis&synthesis when i use the vqm file generated in other project

NOW I use FPGA STRATIX IV E and this option isn't accessible .

So is there any other method to generate a post mapping netlist file?

Thank you for your help

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Open the assignments -> Design Partition Window, then right click on the top partition and write out a .qxp file. You should be able to add that to the other project like a source file.

    (An easier way is to put a partition on that hierarchy in the new project, and just set it to post-synthesis. It will synthesize it the first time, but shouldn't on subsequent compiles as long as the contents don't change.)