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Altera_Forum's avatar
Altera_Forum
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8 years ago

How can we do pipelining between CPU thread and FPGA kernel?

I want to do pipelined processing between the host and FPGA. Say I have kernel0 implemented on host while kernel1 implemented on FPGA. Kernel0 may generate 1000 data where kernel1 will process t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

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Many thanks, I completely missed this section.

Any idea on the latency/throughput compared with typical global memory accesses ?

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If you have access to ACM, check this paper from Altera regarding implementation of host pipes:

https://dl.acm.org/citation.cfm?id=3078182