How can we do pipelining between CPU thread and FPGA kernel?

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You want live in XXII Century ?

This may be simple with "smart" commands of read memory on both sides -- only after write need address or in this moment.

CPU and FPGA may have "spy" blocks on global bus that see all transaction on common "memory".

If write address is near and greater than waited -- read memory, if equal -- get data direct from bus on fly.

Your FPGA may give to CPU a region of addresses that put all writing data to FIFO.

This all is`nt OpenCL. However, Intel may add this possibility to channel input.

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Yes, you are right. I see the problem.

Thank you

Cheng Liu