How can one generate a 100 MHz and 200 MHz clocks that is edge aligned with the 200 MHz tx_clkout output of the Altera transceiver PMA IP?

Hi folks,

I have a little bit of a problem with some derived clock settings. I'm working on a project where we are using register mode data transfers to the PMA via PCS Direct. The PMA and the data feeding logic therefore must be clocked by the tx_clkout of the Altera transceiver IP. However, for another reason, I must have a slower running clock (100 MHz) edge aligned to the faster 200 MHz clock. I know that we can use an IOPLL hooked up to the same reference clock source to generate the two clock rates I need. However, I'm struggling to coax Quartus to make it edge aligned with the tx_clkout of the PMA. The edge alignment is necessary because we want to avoid a FIFO. Has anyone done this before? And are there any special Quartus settings, SDC commands or special things we need to do to do what we want?