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JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

When you implement your design (6-Input NAND gate) it will directly optimize the design and use LUT chain interconnect when necessary. There is no way to manually implement it.

  • SYosh17's avatar
    SYosh17
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    Thank you for answering.

    I implement very simple example of 6-input NAND. The place and route result of this design using 2 LE, which placed different LAB. I think it does not use LUT chain interconnect. I attached the project files.

    Is there any example using LUT chain interconnect?