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ONors's avatar
ONors
Icon for New Contributor rankNew Contributor
7 years ago

How can I use altera_avalon_sc_fifo in a VHDL simulation?

I use altera_avalon_sc_fifo (Avalon_ST Single Clock FIFO) in qsys. When I generate HDL I select VHDL for simulation I get <qsys_name>/altera_avalon_sc_fifo_161/sim/altera_avalon_sc_fifo.v and <qsys_n...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

If possible can you share the project ?

Issue may be due to bench.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)