How can I use altera_avalon_sc_fifo in a VHDL simulation?

I use altera_avalon_sc_fifo (Avalon_ST Single Clock FIFO) in qsys. When I generate HDL I select VHDL for simulation I get <qsys_name>/altera_avalon_sc_fifo_161/sim/altera_avalon_sc_fifo.v and <qsys_n...