How can I split bus in Quartus?

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The problem is that the 2D bus coming out int8 is getting separated to single wires when they connect to nios_system. When you connect those buses to nios_system use the bus drawing option (thick line) because right now you are trying to funnel 12 wires into 1 which is why Quartus is complaining.

I have never tried round 2D bus lines in a schematic before so I'm not certain what indexing you need to use so you might need to use adc[0][11..0], adc[1][11..0], etc... when connecting to nios_system.

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Thank you, BadOmen. you are right and I managed to achieve this, but I am wondering if we could do the opposite? Instead of splitting single line into many signals, how could I merge many signals to single? the reason I am asking is because in the Qsys, I am using twelve input parallel ports (lets name them pio1 to pio12), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio12 from the nios ii system symbol so I can connect these pios to other blocks in my bdf.

My question is, how to vectorize these pio1 to pio12? Instead of seeing all twelve pios one line by one line coming out from the Nios system symbol, what should I do in order to group all these twelve pios so that I only see one instead of twelve? From the one pio that I see, I can name it pio[1..12][1..12], the first bracket means pio1 to pio12, the second bracket means bit1 to bit 12 because each parallel port has 12 bits.

Thank you in advance, appreciate any input