How can I split bus in Quartus?

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If I understood the question correctly then do this:

1) From the QA port draw a single line out that doesn't connect to anything and name it "counter[0]"

2) Do the same with the QB, QC, and QD ports and name them counter[1], counter[2], and counter[3]

3) Draw a bus line to the SOPC Builder system that doesn't connect to anything else and name it "counter[3..0]"

Quartus II knows that those individual signals connect to the SOPC Builder system since they share the same name. Alternatively you could just wire the four outputs into a bus line within the counter and not have to worry about doing this in the schematic.

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Hi BadOmen, I face similar problem so I came across this post:

Instead of creating twelve Parallel input output ports (PIO) in Qsys/SOPC, is there any way I could vectorise many parallel input output ports (12 PIOs for example) into a single component in Qsys or SOPC?

Each PIO consists of 12 bits.

After creating the Nios system, I am going to include the Nios system block in the schematic in Quartus.

I need to feed the twelve PIOs into one single bus line in the schematic block in Quartus II. So I thought I want to combine the twelves PIOs so that in the NIos system block, it will only show one PIO instead of twelve.

I attached the image:

adc[1..12][11..0] is the 12 signals, each with 12 bits

in Nios system block, adc_v1_export is single signal, with 12 bits

I want to connect

What I have tried : I followed the advice in this thread but i got the following error (Error (275024): Width mismatch in port "adc_v1_export[11..0]" of instance "inst14" and type nios_system -- source is ""adc[0]"").

Thank you