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sli30's avatar
sli30
Icon for New Contributor rankNew Contributor
7 years ago

How can I see the place&route on FPGA for OpenCL file?

Dear all, Typically for RTL code, we can use chip planner in Quartus to see the resource place&route. My question is now I'm using commend aoc to generate the *.aocx file (aoc *.cl -o *.aocx). It wi...
HRZ's avatar
HRZ
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

I don't think the OpenCL compiler puts any placement restrictions on the kernels; hence, the placer is allowed to put any part of any kernel on any section of the FPGA. In other words, a multi-kernel design will be placed and routed as a single design and I doubt it would be possible to tell the different kernels apart after placement and routing.