Hooking up Mentor AXI BFM to Platform Designer Simulation

Have you Generate VHDL simulation and synthesis files for your system? Which Quartus version are you using? (pro / standard)

You can try to go through the simulation flow and check is there anything amiss.

Reference (pro): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf