Homemade TestBench attmept

Just for completeness of this forum, my output waveform is below along with the testbench file, and the module under test. Thanks for the assist.

http://hphotos-snc3.fbcdn.net/hs047.snc3/13453_10150214833435055_754135054_13041362_2638503_n.jpg

-------------------------------------- Module Code ------------------------------------------------>

Library ieee;
Use ieee.std_logic_1164.all;
------------------------------------>
Entity Freq_Div_1 is
  Generic(n : integer := 4);
  
  Port(
        clk : IN std_logic :='0'; 
        out1,out2 : out std_logic :='0'
      );
End Freq_Div_1;
------------------------------------>
Architecture Div of Freq_Div_1 is
  Signal count1 : Integer Range 0 to 7 :=1 ;
  Signal count2b : Integer Range 0 to 7 :=1;
  Signal out1_int : std_logic :='1';
  Signal out2_int : std_logic :='1';
  
Begin
  
  Process (clk)
      Variable count2 : integer range 0 to 7 :=0;
    Begin
      if (clk'EVENT and clk='1') then
       count1 <= count1 + 1;
       count2 := count2 + 1;
       count2b <= count2;
       if ( count1 = n) then
         out1_int <= not out1_int;
         out1 <= out1_int;
         count1 <= 1;
       end if;
       if(count2 = 2) then
         out2_int <= not out2_int;
         out2 <= out2_int;
         count2 := 0;
       end if;
   end if;
 End Process;
End Div;
 

----------------------------------- Test Bench Code ---------------------------------------------->

Library ieee;
Use ieee.std_logic_1164.all;
------------------------------------->
Entity tFreq_Div_1 is
 
End tFreq_Div_1;
------------------------------------->
Architecture testBench of tFreq_Div_1 is
 
 -- ******** Component ******** ----->
 Component Freq_Div_1
   Port(
        clk : in std_logic;
        out1,out2 : buffer std_logic
    );
  End Component Freq_Div_1;
 --**** Test Signals ******* -------->
  
 Signal clk : std_logic :='0'; 
 Signal out1 : std_logic;
 Signal out2 : std_logic;
 
------------------------------------->
Begin
  dut:Freq_Div_1
  Port MAP
  (
    clk => clk,
    out1 => out1,
    out2 => out2
  );
  
 clk_In : Process 
 Begin
      wait for 10 ns; clk <= not clk;
 End Process clk_In;
 
End testBench;