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Altera_Forum
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14 years ago

hold violation

Hi i'm using Quartus10.1 for startix iV gx evaluation board. during my synthesis i recieve the next info: info: design requires adding a large amount of routing delay for some signals to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks

this is my default configuration

i removed some of the logic i had on the clock tree and it seems to work

even though i would like to check this logic in the fpga