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Altera_Forum's avatar
Altera_Forum
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11 years ago

Hold violation within DSP block

I'm seeing lot of hold violations between several DSP_MULT and DSP_OUT blocks. I have enabled the options such as Optimize hold timing for all paths and Optimize multi-corner timing but that is not helping in fixing the hold violations. I have attached the timing report on the path. Any suggestions to fix this issue would be really helpful.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Another way is if it's inferred, in which case the timing could be fixed if the output registers were pushed into the fabric(that would fix it if it weren't inferred too). Of course, the best way is to get rid of the clock skew...

    --- Quote End ---

    Though I got it fixed by removing the clock skew, I would like to understand how the output registers can be pushed into the fabric. The DSP blocks are inferred from the design.