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Altera_Forum's avatar
Altera_Forum
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11 years ago

Hold violation within DSP block

I'm seeing lot of hold violations between several DSP_MULT and DSP_OUT blocks. I have enabled the options such as Optimize hold timing for all paths and Optimize multi-corner timing but that is not ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It is not clear how a dsp block(mult/add) is wired to 2 clocks because it has one clk port.