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Altera_Forum's avatar
Altera_Forum
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9 years ago

Hold violation on source synchronous clocks

Timing is failing with Hold time negative slack of (-0.098) when going from a 20MHz to a 100MHz clock domain (both clocks are synchronous and generated from the same PLL). This is a cyclone V design...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Is the path fully inside a DSP block? If so, the router can't add delay and the clock skew may be too large. If that's the case, please try to have all the DSP registers use the same clock domain and then transfer between domains in the fabric.

If the path is in the fabric, you could overconstrain it. Add to your .sdc:

if {$::quartus(nameofexecutable) != "quartus_sta"} {

set_min_delay -from [get_clocks REGCLK] -to [get_clocks SCLK] 0.2

}

This constraint will be seen by the fitter so it tries to add more delay, but in timing sign-off you'll have the correct 0ns analysis.