Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHold violation on source synchronous clocks
Timing is failing with Hold time negative slack of (-0.098) when going from a 20MHz to a 100MHz clock domain (both clocks are synchronous and generated from the same PLL). This is a cyclone V design...
Altera_Forum
Honored Contributor
9 years agoThanks Victor.
I am using Clock enables, but I was reading Rysc's TimeQuest user guide and it seemed to suggest that when you open the window, you're generally relaxing the setup relationship but the hold relationship stays at zero, so I was a confused as to whether or not clock enables provide immunity from hold violations due to excessive clock skew for example. Also, when using clock enables, are you supposed to keep the clock enable asserted for the duration of the new data valid window? thanks, Peter