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Altera_Forum's avatar
Altera_Forum
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9 years ago

Hold violation on source synchronous clocks

Timing is failing with Hold time negative slack of (-0.098) when going from a 20MHz to a 100MHz clock domain (both clocks are synchronous and generated from the same PLL). This is a cyclone V design...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi there,

Probably the best way is to resolve this by setting a multi cycle path but you need to take care of it with clock enables or some other functional technique.

Another thing, did you try the Timing Optimization Advisor that the Quartus tool provides to optimize for hold timings?

Thanks,

Victor