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Altera_Forum
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9 years ago

Hold time violation

Hi @ everyone! In our project, lately we get a hold time violation. FPGA: Cyclone V Clk period: 31.25 ns The signals where the violation occurs are intern signals. In the att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I used Quartus 16.0 and synthesized the project twice.

There are no timing violations anymore!

Thanks, Ryan!

Does it also make sense to overconstrain the logic element where the hold time violation occurs? ... instead of overconstraining the whole domain?