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Altera_Forum
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9 years ago

Hold time violation

Hi @ everyone! In our project, lately we get a hold time violation. FPGA: Cyclone V Clk period: 31.25 ns The signals where the violation occurs are intern signals. In the att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thank you very much for your support!

We use Quartus 14.0.

I think, the version is not that old. I would try with it with a newer one, but unfortunately we don't have a license for it yet.