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Altera_Forum's avatar
Altera_Forum
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9 years ago

Hold time violation

Hi @ everyone! In our project, lately we get a hold time violation. FPGA: Cyclone V Clk period: 31.25 ns The signals where the violation occurs are intern signals. In the att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Okay, you're doing everything right. PLL -> Global clock tree, everything looks correct, etc. This shouldn't be failing.

What version of Quartus are you using? You could try overconstraining the domain, although I'm not a fan of doing it for an entire domain. I would try a newer version of Quartus is what you have is old(I've seen numerous times where this occurs due to router overestimating that it met timing and that estimate gets tuned in later versions). To overconstrain, add something like the following to your .sdc:

if {$::quartus(nameofexecutable) != "quartus_sta"} {

set_min_delay 0.020 -from [get_clocks <pll_clock>] -to [get_clocks <pll_clock>]

}

Substitute the <pll_clock> with the name of the clock. You can wildcard it too.

FYI, I don't generally respond to emails for stuff like this. This is not my job function and I'd get swamped doing direct support. I generally just hop on now and then to try and answer a few things and hope others watching/reading learn from it too. (I'm not sure if that was your intent about email, just throwing it out there.) Good luck.