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Altera_Forum
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9 years ago

Hold time violation

Hi @ everyone! In our project, lately we get a hold time violation. FPGA: Cyclone V Clk period: 31.25 ns The signals where the violation occurs are intern signals. In the att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks a lot for your support, Ryan.

I added a new screen shot showing -detail full_path. I hope it can be read better now.

At the FPGA pin 50 MHz input clock is provided.

A Pll generates the 32 MHz (31.25 ns) using that 50 MHz. The 32 MHz are used in the module with the violation.

The .sdc already contains the lines: 

derive_pll_clocks
derive_clock_uncertainty

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