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Altera_Forum
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9 years ago

Hold time violation

Hi @ everyone! In our project, lately we get a hold time violation. FPGA: Cyclone V Clk period: 31.25 ns The signals where the violation occurs are intern signals. In the att...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I have trouble reading that, but it looks like there is a lot of clock skew. Run report_timing again but with the -detail full_path option, which breaks out the clock path info. Then see why they're so different and see if you can fix it(I assume these clocks are related?)