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Rk_Athram
Occasional Contributor
Occasional ContributorHigh Speed Reed solomon intel FPGA IP
Hello,
I am using High speed reed solomon Intel FPGA IP and simulating using model sim for the polynomial 1033 and parallelism of 2 with each symbol being 10bits. I would like to know how do i verify the parity values/check symbols generated from the IP
thank you
RK
3 Replies
ZiYing_IntelFrequent Contributor
Hi RK,
Thanks for submitting the issue. Please do allow me have some time to look into your issue and I will get back to you with findings.
Best regards,
Zi Ying
- ZiYing_Intel
Hi RK,
You may check whether the value is a legal value through the table of parameters, Table 11, pg 23,
- ZiYing_Intel
Hi RK,
Since I have addressed your question and haven't hear any feedback from you, I am now close the case. If you have any question after the case closed, please do feel free to submit another issue.
Best regards,
Zi Ying
