Hi, Im trying to make testbench but i get this error (vsim-7) Failed to open readmem

Why is there a space in your file path? Modelsim and pretty much all tools don't like spaces in paths.

Angel,

Your path seem has space which would make the tool not able to navigate to it. Rename the path without space.

@SyafieqS @sstrell Thanks for replying! I changed the path and now im getting this error

** Error: (vsim-3033) topModule.svo(53678): Instantiation of 'fiftyfivenm_adcblock' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /topModule File: topModule.svo
# Searched libraries:
# D:/fpga19.1/modelsim_ase/altera/verilog/altera_mf
# D:/alteraAsk/topModule/simulation/modelsim/gate_work


Any ideas on what to do?

Perhaps something in this post will help:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Problems-simulating-ADC-in-DE10-Lite-board-using-Quartus-Prime/td-p/698403

Angel,

Are you able to solve the simulation issue?

See if below discussion could be helpful.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Problems-simulating-ADC-in-DE10-Lite-board-using-Quartus-Prime/td-p/698403