hi, i would like to implement a PCIe to PCIe bridge (ArriaV GX) between 2 Hosts (both Root Complex).

thank you for your answer.

i will describe the system i have today: i have a Root Complex Host and a dedicated EP Processor and they are connected to each other with the PCIe interface. the problem i have is that each time i restart the processor i have to shut down and power up the Host to initiate enumeration process. in order to avoid it i wish to change the processor to be Root Complex and add FPGA with 2 PCIe EP Cores to transfer the TLPs between them. this way the Host and the Processor, each will interface one PCIe EP Core and i will not have enumeration problems. the problem i am facing is to find a solution in which the Host and the Processor will not have to change their functionalities (accept changing the Processor to be Root Complex instead of EP) and to transfer the information between them in "Transparent" way. Do you think there is a way to receive TLP from the Host through its corresponding interfacing FPGA PCIe EP Core, manipulate the TLP header in some way, and forward it to the other FPGA PCIe EP Core to be transmitted to the Processor?

thanks,

Oren