Honored Contributor
Honored ContributorThis is my code....
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Project3M2A is
--generic(lower: integer:=1; upper:integer:=127);
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
W : out STD_LOGIC_VECTOR (7 downto 0);
X : out STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0);
Z : out STD_LOGIC_VECTOR (7 downto 0);
LOAD : in STD_LOGIC;
COMPLETE: out STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end Project3M2A;
architecture Behavioral of Project3M2A is
type state_type is (S0,S1,S2,S3,S4,S5,S6,S7);--,S3,S4,S5,S6,S7,S8,S9,S10);
signal state, state_next: state_type;
signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15: signed( 7 downto 0);
signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next,R13_next,R14_next,R15_next: signed( 7 downto 0);--,R12_next,R13_next,R14_next,R15_next: signed( 7 downto 0);
begin
P1: process(clk,rst) is
begin
if rst='0' then
state<=S0;
r1 <= (others => '0');
r2 <= (others => '0');
r3 <= (others => '0');
r4 <= (others => '0');
r5 <= (others => '0');
r6 <= (others => '0');
r7 <= (others => '0');
r8 <= (others => '0');
r9 <= (others => '0');
r10 <= (others => '0');
r11 <= (others => '0');
r12 <= (others => '0');
r13 <= (others => '0');
r14 <= (others => '0');
--r15 <= (others => '0');
elsif(clk'event and clk='1' and load='1') then
state <= S1;
state <=state_next; -- next state update
r1<=r1_next;-- update next state at rising edge of clk
r2<=r2_next;
r3<=r3_next;
r4<=r4_next;
r5<=r5_next;
r6<=r6_next;
r7<=r7_next;
r8<=r8_next;
r9<=r9_next;
r10<=r10_next;
r11<=r11_next;
r12<=r12_next;
r13<=r13_next;
r14<=r14_next;
--r15<=r15_next;
end if;
end process P1;
P2: PROCESS(load,state,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,A,B)
begin
case state is
when S0 =>
r1_next<= SIGNED(A(7 downto 0));
r2_next<= SIGNED(B(7 downto 0));
state_next<=S1;
when S1=>
r3_next<=signed (A) +2;
r4_next<=signed (B)+2;
state_next<= S2;
complete<='1';
when S2=>
r5_next<= signed (r3_next)+2;
r6_next<= signed (r4_next)+2;
state_next<=S3;
when S3=>
r7_next<=signed (r5_next)+2;
r8_next<=signed (r6_next)+2;
state_next<= S4;
when S4=>
r9_next<=signed (r7_next)+2;
r10_next<=signed (r8_next)+2;
state_next<=S5;
when S5=>
r11_next<=signed (r9_next)+2;
r12_next<=signed (r10_next)+2;
state_next<=S6;
when S6 =>
r13_next <=signed (signed(r1_next)* signed(r2_next));
--r14_next <= r3_next*r4_next;
--r15_next <= r5_next*r6_next;
state_next<=S7;
when S7 =>
r14_next <=signed(signed(r3_next)* signed (r4_next));
state_next<=S0;
end case;
end process P2;
W<= std_logic_vector(signed (r13_next));
end Behavioral;
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--use ieee.std_logic_arith.all;
--USE ieee.std_logic_signed.ALL;
--USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY Project3M2A_TBW IS
END Project3M2A_TBW;
ARCHITECTURE behavior OF Project3M2A_TBW IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Project3M2A
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
W : OUT std_logic_vector(7 downto 0);
X : OUT std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(7 downto 0);
Z : OUT std_logic_vector(7 downto 0);
-- P : INOUT std_logic_vector(7 downto 0);
LOAD : IN std_logic;
COMPLETE: OUT std_logic;
RST : IN std_logic;
CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal LOAD : std_logic := '0';
signal RST : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal W : std_logic_vector(7 downto 0);
signal X : std_logic_vector(7 downto 0);
signal Y : std_logic_vector(7 downto 0);
signal Z : std_logic_vector(7 downto 0);
signal COMPLETE: std_logic :='0';
-- Clock period definitions
constant CLK_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Project3M2A PORT MAP (
A => A,
B => B,
W => W,
X => X,
Y => Y,
Z => Z,
LOAD => LOAD,
RST => RST,
CLK => CLK
);
A<="00000001";
B<="00000010";
load<=not load after 40ns;
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='0';
wait for 5ns;
rst<='1';
wait for 10ns;
wait;
end process;
END;
