help!!

this is my waveformhttp://www.alteraforum.com/forum/attachment.php?attachmentid=9698&stc=1

this is my test bench

ARCHITECTURE behavior OF Project3M2A_TBW IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Project3M2A

PORT(

A : IN std_logic_vector(7 downto 0);

B : IN std_logic_vector(7 downto 0);

W : OUT std_logic_vector(7 downto 0);

X : OUT std_logic_vector(7 downto 0);

Y : OUT std_logic_vector(7 downto 0);

Z : OUT std_logic_vector(7 downto 0);

-- P : INOUT std_logic_vector(7 downto 0);

LOAD : IN std_logic;

COMPLETE: OUT std_logic;

RST : IN std_logic;

CLK : IN std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic_vector(7 downto 0) := (others => '0');

signal B : std_logic_vector(7 downto 0) := (others => '0');

signal LOAD : std_logic := '0';

signal RST : std_logic := '0';

signal CLK : std_logic := '0';

--Outputs

signal W : std_logic_vector(7 downto 0);

signal X : std_logic_vector(7 downto 0);

signal Y : std_logic_vector(7 downto 0);

signal Z : std_logic_vector(7 downto 0);

signal COMPLETE: std_logic :='0';

-- Clock period definitions

constant CLK_period : time := 40 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Project3M2A PORT MAP (

A => A,

B => B,

W => W,

X => X,

Y => Y,

Z => Z,

LOAD => LOAD,

RST => RST,

CLK => CLK

);

A<="00000001";

B<="00000010";

load<=not load after 10ns;

-- Clock process definitions

CLK_process :process

begin

CLK <= '0';

wait for CLK_period/4;

CLK <= '1';

wait for CLK_period/4;

end process;

-- Stimulus process

stim_proc: process

begin

rst<='0';

wait for 5ns;

rst<='1';

wait for 10ns;

wait;

end process;

END;

Could it be the clock problem?

http://www.alteraforum.com/forum/attachment.php?attachmentid=9699&stc=1

This waveforms shows that after i did this ------ r13_next <=signed (signed(r1_next)* signed(r2_next));

it gave me output 0 is because it did binary AND operation?

how do i make it to give me the ans 2.

supposed to give me ans of (1*2) = 2.