--- Quote Start ---
The next signals all append 0 to the bottom of the word. Therefore not really doing a lot.
if you want to increment by 2, why not write:
r3_next <= signed(A) + 2;
--- Quote End ---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.All;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Project3M2A is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
W : out STD_LOGIC_VECTOR (7 downto 0);
X : out STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0);
Z : out STD_LOGIC_VECTOR (7 downto 0);
LOAD : in STD_LOGIC;
COMPLETE: out STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end Project3M2A;
architecture Behavioral of Project3M2A is
type state_type is (S0,S1,S2,S3,S4,S5,S6);--,S3,S4,S5,S6,S7,S8,S9,S10);
signal state, state_next: state_type;
signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 7 downto 0);
signal mult1,mult2,mult3,mult4: signed (7 downto 0);
signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12: signed (7 downto 0 );--R3,R4,R5,R6: std_logic_Vector (7 downto 0 );
signal R13,R14,R15,R16,R17,R18,R19,R20: signed (7 downto 0 ); -- Registers for doing X and +
signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0);
signal R13_next,R14_next,R15_next: signed( 7 downto 0);
signal prod1,prod2,prod3: signed (7 downto 0);
begin
P1: process(clk,rst) is
begin
if rst='0' then
state<=S0;
r1 <= (others => '0');
r2 <= (others => '0');
r3 <= (others => '0');
r4 <= (others => '0');
r5 <= (others => '0');
r6 <= (others => '0');
r7 <= (others => '0');
r8 <= (others => '0');
r9 <= (others => '0');
r10 <= (others => '0');
r11 <= (others => '0');
r12 <= (others => '0');
r6 <= (others => '0');
r7 <= (others => '0');
elsif(clk'event and clk='1') then
state <=state_next; -- next state update
r1<=r1_next;-- update next state at rising edge of clk
r2<=r2_next;
r3<=r3_next;
r4<=r4_next;
r5<=r5_next;
r6<=r6_next;
r7<=r7_next;
r8<=r8_next;
r9<=r9_next;
r10<=r10_next;
r11<=r11_next;
r12<=r12_next;
r13<=r13_next;
r14<=r14_next;
end if;
end process P1;
P2: process (load, state,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14, A,B)
begin
r1_next<=r1;-- keep previous data if not updated
r2_next<=r2;
r3_next<=r3;
r4_next<=r4;
r5_next<=r5;
r6_next<=r6;
r7_next<=r7;
r8<=r8_next;
r9<=r9_next;
r10<=r10_next;
r11<=r11_next;
r12<=r12_next;
r13<=r13_next;
r14<=r14_next;
complete<='0';
case state is
when S0 => if load ='1' then
r1_next<= signed (A(7 downto 0));
r2_next<= signed (B(7 downto 0));
state_next<=S1;
complete<='1';
else
state_next<=S0;
end if;
when S1=> if load ='1' then
r3_next<=signed (A) +2;
r4_next<=signed (B) +2;
state_next<= S2;
--complete<='1';
else
state_next<=S1;
end if;
when S2=> if load ='1' then
r5_next<=signed (r3_next)+2;
r6_next<=signed (r4_next)+2;
state_next<=S3;
else
state_next<=S2;
end if;
when S3=> if load ='1' then
r7_next<=signed (r5_next)+2;
r8_next<=signed (r6_next)+2;
state_next<= S4;
else
state_next<=S3;
end if;
when S4=> if load ='1' then
r9_next<=signed (r7_next)+2;
r10_next<=signed (r8_next)+2;
state_next<=S5;
else
state_next<=S4;
end if;
when S5=> if load ='1' then
r11_next<=signed (r9_next)+2;
r12_next<=signed (r10_next)+2;
state_next<=S6;
else
state_next<=S5;
end if;
when S6=>
r13_next<=prod1;
r14_next<=prod2;
state_next<=S0;
end case;
end process p2;
CSA1: prod1 <= mult1*mult2;
CSA2: prod2<= mult3*mult4;
P3: process( state,r1,r2,r3,r4,r13,r14)
begin
case state is
when S6=>
mult1 <=signed (A); --R1,A1
mult2 <=signed (B); --R2,A2
when others =>
mult3<= r3; --R3
mult4 <=r4; -- R4
end case;
end process P3;
W<= std_logic_vector(prod1);
end Behavioral;
I want to multiply them together R1*R2. How do i do it? my testbench doesn't show any waveform
Honored Contributor
