help

I have circuit an transmitter serial asynchronous and I to write VHDL code here is the schema

But there are problems

I have circuit an transmitter serial asynchronous and I to write VHDL code here is the schema

But there are problems

Hi.:)

The problem here is how I write the program, which includes all units ,I have an example but that does not work

Sorry, I did not mean this

Is the design of the circuit properly?

But I want to know how to write paketage, because the program did not know all the signs

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First of all I would recommend you download quartus and stop using MAX Plus 2. It isnt very good with VHDL, or much else.

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I agree. The faults indicated by MaxPlus 2 are however reported correctly.

Reviewing your top entity emettuer.vhd reveals some misunderstandings of how to instantiate components.

- All signals appearing on the right side of the port maps must be defined in the respective architecture, which you didn't.

- you are using different names for the same signal on the right side of the port maps

Fixing this point should remove most or all reported errors. It may be reasonable to look up the component instantiation topic in a text book or tutorial to get more clarity.

The basic structure of your design seems nevertheless correct. There are questionable points like the divided UART clock, but I think you should try to compile the design and test it in a simulation before thinking about things like this. The general suggestion is to use clock enables instead of divided clocks as far as possible.

Thanks for help

For the program QUARTUS

Asked me the contract and I do not have this contract

At this moment I have MaxPlus 2

The first thing to improve my program got rid of the error signals as I have said to me, left me how I link

work and the overall program

Wait for your answer

Greetings and sincere thanks

//////////////////////////////////////////////////

LIBRARY work;

use work.emetteurElement_package.ALL;----how to report software and connect in my code Which is under the ----

PACKAGE emetteurElement_package IS

component diviseur is

port (clk_in , reset : in std_logic;

clk_div : out std_logic

);

end component diviseur;

component Controle is

PORT (clk , reset : IN STD_LOGIC;

clk_c,fin_tx , go : IN STD_LOGIC;

charge ,decale : OUT STD_LOGIC

);

end component Controle;

component compteur is

port ( clk : in Std_Logic;

incr,rz : in Std_Logic;

cpt : out Std_Logic

);

end component compteur;

component decalage is

PORT (clk, reset : IN STD_LOGIC;

load , shift : IN STD_LOGIC;

serial : IN STD_LOGIC;

dinr : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

tx : OUT STD_LOGIC

);

end component decalage;

component parity is

port (din : in std_logic_vector (7 downto 0);

p_out : out std_logic

);

end emetteurElement_package;

/////////////////////////////////////////////////////

and

////////////////////////////////////////////////////

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.all;

use WORK.emetteurElement_package.ALL,

entity emetteur1 is

port (clk , reset :in std_logic;

go :in std_logic;

din :in std_logic_vector (7 downto 0);

tx :out std_logic

);

end emetteur1;

architecture struc of emetteur1 is

SIGNAL decales : STD_LOGIC;

SIGNAL charges : STD_LOGIC;

SIGNAL cpts : STD_LOGIC;

SIGNAL clk_divs : STD_LOGIC;

SIGNAL bparity : STD_LOGIC;

SIGNAL dins : STD_LOGIC_VECTOR (10 DOWNTO 0);

CONSTANT stopBit_c : STD_LOGIC := '1';

CONSTANT startBit_c : STD_LOGIC := '0';

BEGIN

dins <= bparity & din & startBit_c & stopBit_c;

diviseur_ci: diviseur

port map (clk_in => clk ,

reset => reset ,

clk_div => clk_divs );

controle_ci: Controle

port map ( clk => clk,

reset => reset ,

clk_c => clk_divs ,

fin_tx => cpts,

go => go,

charge => charges,

decale => decales );

decalage_ci: decalage

port map ( clk => clk ,

reset => reset ,

load => charges,

shift => decales,

serial => stopBit_c,

dinr => dins ,

tx => tx );

parite_ci: parity

port map (din => din,

p_out => bparity);

compteur_ci: compteur

port map ( clk => clk,

incr => decales,

rz => charges,

cpt => cpts );

END ARCHITECTURE struc;

////////////////////////////////////////////