help

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First of all I would recommend you download quartus and stop using MAX Plus 2. It isnt very good with VHDL, or much else.

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I agree. The faults indicated by MaxPlus 2 are however reported correctly.

Reviewing your top entity emettuer.vhd reveals some misunderstandings of how to instantiate components.

- All signals appearing on the right side of the port maps must be defined in the respective architecture, which you didn't.

- you are using different names for the same signal on the right side of the port maps

Fixing this point should remove most or all reported errors. It may be reasonable to look up the component instantiation topic in a text book or tutorial to get more clarity.

The basic structure of your design seems nevertheless correct. There are questionable points like the divided UART clock, but I think you should try to compile the design and test it in a simulation before thinking about things like this. The general suggestion is to use clock enables instead of divided clocks as far as possible.