Help with vhdl code

------------------------------STATE MACHINE ---------------------------------
-----------------------------------------------------------------------------
E_FSM_CHAINE :FSM_CHAINE     
   PORT MAP
        ( 
          clk             	   => CLK,
          reset           	   => reset,
          start           	   => START,
          start_out           => START_out,
          START1              => START1,
          START2              => START2,
          START3              => START3,
          DONE_t0             => DONE_t0,
          DONE_t1             => DONE_t1,
          full                => full,
          usedw               => usedw,
          READ                => READ,
          DONE                => DONE_chaine_out ,
          sel                 => sel,
          Mode                => Mode,
          Mode_4              => Mode_4,
          Mode_16             => Mode_16
        );
   -------------------------------------------------------------------------
   -------------------------------------------------------------------------

no this is the component instantiation. You should have a declaration in your architecture, somewhere before the begin

-----------------------------------------------------------
ARCHITECTURE full1 OF CHAINE_TOP_LEVEL IS
----------------------------------------------------------- 
TYPE tableau IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR( 15 DOWNTO 0);
TYPE tableau1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR( 22 DOWNTO 0);
SIGNAL Done,DONE_t1,DONE_t2,DONE_t0,DONE_t3 :STD_LOGIC;
SIGNAL tab_residuel,tabDC,tabHadINV: tableau ;
SIGNAL FIFO_OUT :STD_LOGIC_VECTOR( 344 DOWNTO 0);
SIGNAL FIFO_IN  :STD_LOGIC_VECTOR(344 DOWNTO  0);
SIGNAL coeff_DC :STD_LOGIC_VECTOR( 22 DOWNTO  0);
SIGNAL usedw:STD_LOGIC_VECTOR(3 DOWNTO 0); 
SIGNAL tabQTACinv,tabQTDCINV: tableau1 ;
SIGNAL START1,START2,START3,START4:STD_LOGIC;
SIGNAL READ ,full,empty:std_logic;
SIGNAL cp : integer RANGE 0 TO 15;
SIGNAL  Mode_16,Mode_4,sel  : STD_LOGIC;  
SIGNAL Mode : STD_LOGIC;
   BEGIN 
--------------------------------------------------------------
---------------------------------------------------------------

that doesnt show the component declaration. I guess you're missing it..

Yes - you're missing the component declaration for FSM_CHAINE ( you could have put it in intra_16x16_pkg, but you didnt post that, or you could use direct instantiation instead).

Hi when i try to simulate my file CHAINE_TOP_LEVEL.vhd i get warrning like this

# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE#     Time: 0 ns  Iteration: 0  Instance: /chaine_top_level/e_dequant_ac4x4_top_level/e_dequantization_ac_top_level_13/inst_muxbill#  ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE#     Time: 0 ns  Iteration: 0  Instance: /chaine_top_level/e_dequant_ac4x4_top_level/e_dequantization_ac_top_level_13/inst_muxbill#  ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE#     Time: 0 ns  Iteration: 0  Instance: /chaine_top_level/e_dequant_ac4x4_top_level/e_dequantization_ac_top_level_13/inst_muxbill#  ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
. . . 
. . . 

The warning isnt in the top level - look where it is from the hierarchy. But all it is is that you didnt initialise inst_muxbill in the e_dequantization_ac_top_level_13 module. It's trying to compare "UUUUUUUU" to something else. It wont be a problem unless it doesnt go away. You can turn this warning off in the simulation/runtime options "Suppress messages from IEEE packages"

Its not a problem, just a warning that the signals are uninitialised. It shouldnt be a problem if the code is connected correctly.