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How about your component declaration for FSM_CHAINE in CHANE_TOP_LEVEL.vhd ?
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------------------------------STATE MACHINE ---------------------------------
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E_FSM_CHAINE :FSM_CHAINE
PORT MAP
(
clk => CLK,
reset => reset,
start => START,
start_out => START_out,
START1 => START1,
START2 => START2,
START3 => START3,
DONE_t0 => DONE_t0,
DONE_t1 => DONE_t1,
full => full,
usedw => usedw,
READ => READ,
DONE => DONE_chaine_out ,
sel => sel,
Mode => Mode,
Mode_4 => Mode_4,
Mode_16 => Mode_16
);
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Honored Contributor
